1. Field of the Invention
The present invention relates in general to a probe card assembly for interconnecting test equipment to an integrated circuit die to be tested, and in particular to a probe card assembly that implements each signal path as a high-bandwidth, low-distortion, impedance-matched filter structure between the test equipment and the die.
2. Description of Related Art
An integrated circuit (IC) die typically includes a set of bond pads on its upper surface acting as input/output terminals for the integrated circuit die. When an IC die is packaged, its bond pads provide points of connection for bond wires or other structures that link the IC to external circuits. These bond pads may also provide access points to an IC tester when testing an IC die before it is separated from a wafer and packaged.
An IC tester typically includes a separate channel for each terminal of an IC to be tested, and during a test each channel may transmit a test signal to the IC terminal or may receive and process an IC output signal appearing at the IC terminal. Each channel is typically implemented on a separate circuit board mounted in a relatively large chassis called a xe2x80x9ctest headxe2x80x9d. The tester normally includes a probe card assembly for providing signal paths between the circuit boards mounted in the test head and the IC""s bond pads.
PCT published application WO 96/15458, published May 23, 1996 (incorporated herein by reference) describes a high performance probe card assembly including a set of three separate layers stacked vertically under the test head. One layer of the assembly, a xe2x80x9cprobe cardxe2x80x9d mounted on the probe head, provides points of contact on its surface for pogo pin connectors extending from the circuit boards mounted in the test head. The pogo pins act as input and/or output terminals for the test equipment implemented by those circuit boards. A xe2x80x9cspace transformerxe2x80x9d layer of the probe card assembly includes a set of probes on its underside for contacting the bond pads on the upper surface of the die. An xe2x80x9cinterposerxe2x80x9d board residing between the probe card and the space transformer provides signal routing paths between the probe card and the space transformer therebetween through spring contacts on its surfaces for contacting pads on facing surfaces of the probe card and space transformer.
To test a die at high frequencies it is helpful to position test equipment as closely as possible to the bond pads of the IC being tested so as to reduce the amount of time signals require to travel between the test equipment and the IC""s bond pads. Since the circuit boards in the test head are much larger than the IC die they are to test, the pogo pins through which the circuit boards send and receive signals are necessarily distributed over a much wider horizontal area than the bond pads on the die being tested. Thus the probe assembly must not only route signals vertically between the bond pads and the pogo pins, it also must also route them horizontally. The probes, pogo pins, spring contracts between the various boards of the assembly, and vias within those boards move test signals vertically between the bond pads and the tester circuits. Microstrip traces on the surfaces or layers of the various boards of the probe assembly route those signals horizontally.
One of the reasons tester designers want to minimize the length of the signal paths between the bond pads and the circuits is to minimize delay and impedance discontinuities in those signal paths. When those paths carry high frequency test and IC output signals, impedance discontinuities in the signal path can attenuate and distort those signals. The inherent series inductance and shunt capacitance of the signal routing paths are primary sources of impedance continuities that can lead to signal distortion.
The typical approach to reducing the amount of signal distortion and attenuation caused by the interconnect system has been to minimize signal path lengths and to match transmission line impedances. In doing so, designers typically try to minimize the physical size of the tester circuits, at least in the horizontal plane, so that they can be packed into a smaller horizontal space above or below the IC under test. This minimizes the horizontal distance that signals must travel between the test equipment and the IC bond pads they access. Designers also try to minimize signal path lengths in the interconnect system by making the probe card assembly as thin as possible in the vertical direction, for example by providing probes and pogo pins that are as short as possible, by making the probe card, interposer and space transformer as thin as possible, and by providing spring contacts or other contact structures between those boards that are as short as possible.
Another approach to reducing signal distortion in the signal paths between IC bond pads and the test equipment accessing them has been to minimize the amount of shunt capacitance in those signal paths. Capacitance can be reduced by appropriately choosing physical characteristics of the probes and the various layers of the probe card assembly including the size of the traces, their spacing from ground planes, and the dielectric nature of the insulating material forming those probe card assembly layers. Since vias, conductors passing vertically through the probe card, interposer and space transformer are also a source of shunt capacitance, probe card assembly designers typically structure vias so as minimize their capacitance, typically by providing a relatively wide hole through any ground or power plane through which they pass, since the capacitance of a signal path is inversely related to distance between the signal path and any ground or power planes.
Minimizing interconnect system signal path lengths, minimizing inductance and capacitances of those signal paths, and matching transmission line impedances throughout those signal paths, can help increase the bandwidth, flatten frequency response and reduce the signal distortion. But it is not possible to reduce signal path lengths to zero or to completely eliminate probe card assembly signal path inductance and capacitance. Thus some level of signal distortion and attenuation is inevitable when signal frequencies are sufficiently high. Since distortion and attenuation increase with signal frequency, such signal distortion and attention provide a barrier to accurate high frequency testing.
What is needed is a way to substantially improve the frequency response of signal paths though a probe card assembly so as to reduce distortion and attenuation of signals below a level that can be provided by simply minimizing the lengths and impedances of those signal paths.
The present invention is an improvement to conventional probe card assemblies of the type that interconnect bond pads of an integrated circuit (IC) die to IC test equipment installed in a test head of an integrated circuit tester. In accordance with the invention, each signal path is arranged and adapted to provide a filter function that optimizes relevant characteristics of the path""s frequency response and impedance characteristics by appropriately adjusting the magnitudes of its shunt capacitance and series inductance relative to one another. For example when the test equipment and the die communicate using a low frequency analog signal where it is most important to avoid distortion, the xe2x80x9coptimalxe2x80x9d frequency response of the signal path conveying that signal may have a narrow, but maximally flat, pass band. Or, as another example, when the test equipment and die communicate via a high frequency digital signal, the optimal frequency response may have a maximally wide passband. By appropriately distributing and adjusting the inductance and capacitance of a signal path though a probe card assembly in accordance with the invention, rather than trying to simply minimize them or treat them as transmission line segments, substantial improvement in probe card assembly frequency response is obtained.
It is accordingly an object of the invention to provide a system for interconnecting test equipment to terminals of an integrated circuit device wherein the frequency response and impedance matching characteristics of the interconnect system are optimized for the nature of signals passing therebetween.
The concluding portion of this specification particularly points out and distinctly claims the subject matter of the present invention. However those skilled in the art will best understand both the organization and method of operation of the invention, together with further advantages and objects thereof, by reading the remaining portions of the specification in view of the accompanying drawing(s) wherein like reference characters refer to like elements.